
// Library name: Project
// Cell name: NAND
// View name: schematic
subckt NAND AN AP BN BP HiOut LoOut VDD\+ VDD\- VSS\+ VSS\-
    M3 (net9 BN VSS\- VSS\-) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
    M2 (LoOut AN net9 VSS\-) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
    M1 (net17 BN VSS\+ VSS\+) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
    M0 (HiOut AN net17 VSS\+) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
    M7 (HiOut BP VDD\+ VDD\+) PMOS_VTL w=180.0n l=50n as=1.89e-14 \
        ad=1.89e-14 ps=390.0n pd=390.0n ld=105n ls=105n m=1
    M6 (HiOut AP VDD\+ VDD\+) PMOS_VTL w=180.0n l=50n as=1.89e-14 \
        ad=1.89e-14 ps=390.0n pd=390.0n ld=105n ls=105n m=1
    M5 (LoOut BP VDD\- VDD\-) PMOS_VTL w=180.0n l=50n as=1.89e-14 \
        ad=1.89e-14 ps=390.0n pd=390.0n ld=105n ls=105n m=1
    M4 (LoOut AP VDD\- VDD\-) PMOS_VTL w=180.0n l=50n as=1.89e-14 \
        ad=1.89e-14 ps=390.0n pd=390.0n ld=105n ls=105n m=1
ends NAND
// End of subcircuit definition.

// Library name: Project
// Cell name: NAND_TB
// View name: schematic
I16 (net0123 net0195 net0123 net0195 net0121 net0122 net44 net3 net42 \
        net1) NAND
I15 (net0133 net0134 net0133 net0134 net0123 net0195 net44 net3 net42 \
        net1) NAND
I14 (net0143 net0144 net0143 net0144 net0133 net0134 net44 net3 net42 \
        net1) NAND
I13 (net0153 net0154 net0153 net0154 net0143 net0144 net44 net3 net42 \
        net1) NAND
I12 (net0163 net0164 net0163 net0164 net0153 net0154 net44 net3 net42 \
        net1) NAND
I11 (net0173 net0174 net0173 net0174 net0163 net0164 net44 net3 net42 \
        net1) NAND
I8 (net0211 net0212 net0211 net0212 net0201 net0202 net44 net3 net42 net1) \
        NAND
I9 (net0201 net0202 net0201 net0202 net0191 net0192 net44 net3 net42 net1) \
        NAND
I10 (net0191 net0192 net0191 net0192 net0173 net0174 net44 net3 net42 \
        net1) NAND
I7 (net0221 net0222 net0221 net0222 net0211 net0212 net44 net3 net42 net1) \
        NAND
I6 (net0121 net0122 net0121 net0122 net0221 net0222 net44 net3 net42 net1) \
        NAND
V3 (net1 0) vsource dc=0 type=dc
V2 (net42 0) vsource dc=2*delv type=dc
V1 (net3 0) vsource dc=vdd type=dc
V0 (net44 0) vsource dc=vdd + 2*delv type=dc
